The invention relates to the field of microprocessor architectures. Microprocessor designers are continually striving to improve microprocessor performance, designing microprocessor architectures that provide, for example, increased computational abilities, increased operating speeds, reduced power consumption, and/or reduced cost. With many previous microprocessor architectures, it has become increasingly difficult to improve microprocessor performance by increasing their operating frequency. As a result, many newer microprocessor architectures have focused on parallel processing to improve performance.
One parallel processing technique employed in microprocessor architectures is multiple processing cores. This technique utilizes multiple independent processors, referred to as cores, operating in parallel to execute software applications. Two or more processing cores may be implemented within the same integrated circuit die, within multiple integrated circuit dies integrated within the same integrated circuit package, or a combination of these implementations. Typically, multiple processing cores share a common interface and may share other peripheral resources.
Microprocessors typically operate much faster than typical memory interfaces. Additionally, many types of electronic memory have a relatively long latency time period between the time when a processor requests data and the time the requested data is received. To minimize the time a microprocessor spends idle and waiting for data, many microprocessors use cache memory to store a temporary copy of program instructions and data. Typical cache memory is highly integrated with a microprocessor, often within the same integrated circuit die. As a result, cache memory is very fast and has low latency. However, this tight integration limits the size of the cache memory.
Typical microprocessors employ a multiple-level cache architecture. A processor typically includes a first level of cache memory, referred to as L1 cache, which is very tightly integrated with the processor to provide high speed and very low latency, but is relatively small. A processor also typically includes a second level of cache memory, referred to as L2 cache, which is less tightly integrated with the processor, thereby operating at slower speed and higher latency, but having a larger capacity. Some processors have additional cache levels as well. Typically, data most likely to be used by a processor is preferably stored in the L1 cache, with the L2 cache and other optional caches acting as a fall-back for additional data.
The use of multiple-level cache architectures improves performance, but also consumes a large number of transistors, and hence increases the cost and power consumption of the microprocessor. These drawbacks are exacerbated in multiple core architectures, which, in addition to requiring large numbers of transistors for each core, may also require separate L1 and/or L2 caches for each core.
It is therefore desirable for a multiple core processor to utilize cache memory efficiently to provide improved performance and reduced power consumption for a given amount of chip area. This allows for multiple core processors to provide improved performance for the same cost or to provide the same performance for a reduced cost as prior types of architectures.